SE97B_1
?NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 27 January 2010
26 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
3
EOCTL
EVENT
Output Control.
0 EVENT
output disabled (default)
1 EVENT
output enabled
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
2
CVO
Critical Event Only.
0 EVENT
output on Alarm or Critical temperature event (default)
1 EVENT
only if temperature is above the value in the critical
temperature register
When the alarm window lock bit is set, this bit cannot be altered until
unlocked.
1
EP
EVENT
Polarity.
0 active LOW (default)
1 active HIGH. When either of the Critical Trip or Alarm Window lock
bits is set, this bit cannot be altered until unlocked.
When the EP (EVENT
Polarity) bit is changed, the EVENT
output would
immediately change state on the SE97B. A new Shutdown mode has been
added on the SE97B with two states defined by the SMBus register
EventSleepState = 0. Freeze state of EVENT
output and
EventSleepState = 1: de-asserted state of EVENT
output. So now if the EP
bit changes, the EVENT
output state will change immediately even during
shutdown. It will not wait for the part to do a new temperature conversion
after coming out of shutdown. Changes to all other bits in the CONFIG
register and the SMBus register take effect after a new temperature
conversion happens when the part comes out of shutdown. The EP bit is not
related to temperature conversion or readings or if the part is in shutdown or
active.
Remark: In Shutdown mode, when DisableTimeout = 1 or if
DisableTimeout = 0 and Enable SDIO = 0, the EVENT
Polarity bit will not
take effect immediately, but will updated after it comes out of shutdown.
0
EMD
EVENT
Mode.
0 comparator output mode (default)
1 interrupt mode
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
Table 13. Configuration register (address 01h) bit description &continued
Bit
Symbol
Description
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